The present invention relates to charge-trapping memories, and more particularly to the structure of charge-trapping dielectric.
The state of a charge trapping memory cell is defined by electric charge stored in the cell's charge-trapping dielectric (e.g. silicon nitride). Reliable operation requires good control over storing and erasing the charge in the charge-trapping dielectric. For example, if the charge cannot be reliably erased, the memory characteristics gradually change, and the memory may become inoperable after a small number of the programming/erase cycles. See U.S. Pat. No. 7,067,373 B2, issued Jun. 27, 2006 to Shukuri. The erase reliability can be improved by increasing the erase time, but this is undesirable if fast operation is needed.